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Freescale Semiconductor Data Sheet: Technical Data
MPC5200BDS Rev. 1, 1/2006
MPC5200B Data Sheet
NOTE The information in this document is subject to change. For the latest data on the MPC5200B, visit www.mobilegt.com and proceed to the MPC5200B Product Summary Page.
Table of Contents
1 2 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical and Thermal Characteristics . . . . . . . . . 6 3.1 DC Electrical Characteristics . . . . . . . . . . . . . 6 3.2 Oscillator and PLL Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 AC Electrical Characteristics . . . . . . . . . . . . 14 Package Description . . . . . . . . . . . . . . . . . . . . . . 61 4.1 Package Parameters . . . . . . . . . . . . . . . . . . 61 4.2 Mechanical Dimensions. . . . . . . . . . . . . . . . 61 4.3 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . 63 System Design Information. . . . . . . . . . . . . . . . . 68 5.1 Power Up/Down Sequencing. . . . . . . . . . . . 68 5.2 System and CPU Core AVDD Power Supply Filtering. . . . . . . . . . . . . . . . . 70 5.3 Pull-up/Pull-down Resistor Requirements . . 70 5.4 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Ordering Information . . . . . . . . . . . . . . . . . . . . . . 75 7 Document Revision History . . . . . . . . . . . . . 76
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5
1
Overview
6
The MPC5200B integrates a high performance MPC603e series e300 core with a rich set of peripheral functions focused on communications and systems integration. The e300 core design is based on the PowerPC(R) core architecture. MPC5200B incorporates an innovative BestComm I/O subsystem, which isolates routine maintenance of peripheral functions from the embedded e300 core. The MPC5200B contains a SDRAM/DDR Memory Controller, a flexible External Bus Interface, PCI Controller, USB, ATA, Ethernet, six
(c) Freescale Semiconductor, Inc., 2006. All rights reserved.
Features
Programmable Serial Controllers (PSC), I2C, SPI, CAN, J1850, Timers, and GPIOs.
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Features
MPC603e series e300 core -- Superscalar architecture -- 760 MIPS at 400 MHz (-40 to +85 oC) -- 16 k Instruction cache, 16 k Data cache -- Double precision FPU -- Instruction and Data MMU -- Standard and Critical interrupt capability SDRAM / DDR Memory Interface -- up to 133-MHz operation -- SDRAM and DDR SDRAM support -- 256-MByte addressing range per CS, two CS available -- 32-bit data bus -- Built-in initialization and refresh Flexible multi-function External Bus Interface -- Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices -- 8 programmable Chip Selects -- Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address -- Short or Long Burst capable -- Multiplexed data access using 8/16/32 bit databus with up to 25-bit address Peripheral Component Interconnect (PCI) Controller -- Version 2.2 PCI compatibility -- PCI initiator and target operation -- 32-bit PCI Address/Data bus -- 33- and 66-MHz operation -- PCI arbitration function ATA Controller -- Version 4 ATA compatible external interface--IDE Disk Drive connectivity BestComm DMA subsystem -- Intelligent virtual DMA Controller -- Dedicated DMA channels to control peripheral reception and transmission -- Local memory (SRAM 16 kBytes)
MPC5200B Data Sheet, Rev. 1
Key features are shown below.
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2
Freescale Semiconductor
Features
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6 Programmable Serial Controllers (PSC), configurable for the following: -- UART or RS232 interface -- CODEC interface for Soft Modem, Master/Slave CODEC Mode, I2S and AC97 -- Full duplex SPI mode -- IrDA mode from 2400 bps to 4 Mbps Fast Ethernet Controller (FEC) -- Supports 100Mbps IEEE 802.3 MII, 10 Mbps IEEE 802.3 MII, 10 Mbps 7-wire interface Universal Serial Bus Controller (USB) -- USB Revision 1.1 Host -- Open Host Controller Interface (OHCI) -- Integrated USB Hub, with two ports. Two Inter-Integrated Circuit Interfaces (I2C) Serial Peripheral Interface (SPI) Dual CAN 2.0 A/B Controller (MSCAN) -- Motorola Scalable Controller Area Network (MSCAN) architecture -- Implementation of version 2.0A/B CAN protocol -- Standard and extended data frames J1850 Byte Data Link Controller (BDLC) -- J1850 Class B data communication network interface compatible and ISO compatible for low speed (<125 kbps) serial data communications in automotive applications. -- Supports 4X mode, 41.6 kbps -- In-frame response (IFR) types 0, 1, 2, and 3 supported Systems level features -- Interrupt Controller supports four external interrupt request lines and 47 internal interrupt sources -- GPIO/Timer functions - Up to 56 total GPIO pins (depending on functional multiplexing selections) that support a variety of interrupt/WakeUp capabilities. - Eight GPIO pins with timer capability supporting input capture, output compare, and pulse width modulation (PWM) functions -- Real-time Clock with one-second resolution -- Systems Protection (watch dog timer, bus monitor) -- Individual control of functional block clock sources -- Power management: Nap, Doze, Sleep, Deep Sleep modes -- Support of WakeUp from low power modes by different sources (GPIO, RTC, CAN)
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MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 3
Features
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Test/Debug features -- JTAG (IEEE 1149.1 test access port) -- Common On-chip Processor (COP) debug port On-board PLL and clock generation
Figure 1 shows a simplified MPC5200B block diagram.
MPC5200B Data Sheet, Rev. 1 4 Freescale Semiconductor
SDRAM / DDR
Systems Interface Unit (SIU) 603 Real-Time Clock System Functions Interrupt Controller GPIO/Timers SDRAM / DDR Memory Controller
Freescale Semiconductor
e300 Core
Local Plus Controller Local Bus PCI Bus Controller
JTAG / COP Interface SRAM 16K
Reset / Clock Generation
BestComm DMA
Figure 1. Simplified Block Diagram--MPC5200B ATA Host Controller CommBus SPI USB 2x I2C 2x J1850 Ethernet PSC 6x
MPC5200B Data Sheet, Rev. 1
MSCAN 2x
Features
5
Electrical and Thermal Characteristics
3
3.1
3.1.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
Absolute Maximum Ratings
The tables in this section describe the MPC5200B DC Electrical characteristics. Table 1 gives the absolute maximum ratings.
Table 1. Absolute Maximum Ratings(1)
Characteristic Supply voltage - e300 core and peripheral logic Supply voltage - I/O buffers Supply voltage - System APLL Supply voltage - e300 APLL Input voltage (VDD_IO) Input voltage (VDD_MEM_IO) Input voltage overshoot Input voltage undershoot Storage temperature range Sym VDD_CORE VDD_IO, VDD_MEM_IO SYS_PLL_AVDD CORE_PLL_AVDD Vin Vin Vinos Vinus Tstg Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 - - -55 Max 1.8 3.6 2.1 2.1 VDD_IO + 0.3 VDD_MEM_IO + 0.3 1.0 1.0 150 Unit V V V V V V V V
oC
SpecID D1.1 D1.2 D1.3 D1.4 D1.5 D1.6 D1.7 D1.8 D1.9
NOTES: 1 Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage.
3.1.2
Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Characteristic Sym VDD_CORE VDD_IO VDD_MEM_IOSDR VDD_MEM_IODDR SYS_PLL_AVDD CORE_PLL_AVDD Vin VinSDR Min (1) 1.42 3.0 3.0 2.42 1.42 1.42 0 0 Max (1) 1.58 3.6 3.6 2.63 1.58 1.58 VDD_IO VDD_MEM_IOSDR Unit V V V V V V V V SpecID D2.1 D2.2 D2.3 D2.4 D2.5 D2.6 D2.7 D2.8
Table 2 gives the recommended operating conditions.
Supply voltage - e300 core and peripheral logic Supply voltage - standard I/O buffers Supply voltage - memory I/O buffers (SDR) Supply voltage - memory I/O buffers (DDR) Supply voltage - System APLL Supply voltage - e300 APLL Input voltage - standard I/O buffers Input voltage - memory I/O buffers (SDR)
MPC5200B Data Sheet, Rev. 1 6 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 2. Recommended Operating Conditions (continued)
Characteristic Input voltage - memory I/O buffers (DDR) Ambient operating temperature range Die junction operating temperature
(2)
Sym VinDDR TA Tj TA Tj
Min (1) 0 -40 -40 -40 -40
Max (1) VDD_MEM_IODDR +85 +115 +105 +125
Unit V
oC o o o
SpecID D2.9 D2.10 D2.12 D2.10 D2.12
range(2)
C C C
Ambient operating temperature range(3) Die junction operating temperature range(3)
NOTES: 1 These are recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed. 2 Maximum e300 core operating frequency is 400 MHz. 3 Maximum e300 core operating frequency is 266 MHz.
3.1.3
DC Electrical Specifications
Table 3 gives the DC Electrical characteristics for the MPC5200B at recommended operating conditions (see Table 2).
Table 3. DC Electrical Specifications
Characteristic Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input high voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input low voltage Input leakage current Condition Input type = TTL VDD_IO/VDD_MEM_IOSDR Input type = TTL VDD_MEM_IODDR Input type = PCI VDD_IO Input type = SCHMITT VDD_IO SYS_XTAL_IN RTC_XTAL_IN Input type = TTL VDD_IO/VDD_MEM_IOSDR Input type = TTL VDD_MEM_IODDR Input type = PCI VDD_IO Input type = SCHMITT VDD_IO SYS_XTAL_IN RTC_XTAL_IN Vin = 0 or VDD_IO/VDD_IO_MEMSDR
(depending on input type (1) )
Sym VIH VIH VIH VIH CVIH CVIH VIL VIL VIL VIL CVIL CVIL IIN
Min 2.0 1.7 2.0 2.0 2.0 2.0 -- -- -- -- -- -- --
Max -- -- -- -- -- -- 0.8 0.7 0.8 0.8 0.8 0.8 +2
Unit V V V V V V V V V V V V A
SpecID D3.1 D3.2 D3.3 D3.4 D3.5 D3.6 D3.7 D3.8 D3.9 D3.10 D3.11 D3.12 D3.13
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 7
Electrical and Thermal Characteristics
Table 3. DC Electrical Specifications (continued)
Characteristic Input leakage current Input leakage current Input current, pullup resistor Condition SYS_XTAL_IN Vin = 0 or VDD_IO RTC_XTAL_IN Vin = 0 or VDD_IO PULLUP VDD_IO Vin = 0 PULLUP_MEM VDD_IO_MEMSDR Vin = 0 PULLDOWN VDD_IO Vin = VDD_IO IOH is driver dependent(2) VDD_IO, VDD_IO_MEMSDR IOH is driver dependent(2) VDD_IO_MEMDDR IOL is driver dependent(2) VDD_IO, VDD_IO_MEMSDR IOL is driver dependent(2) VDD_IO_MEMDDR Sym IIN IIN IINpu Min -- -- 40 Max +10 +10 109 Unit A A A SpecID D3.14 D3.15 D3.16
Input current, pullup resistor - memory I/O buffers Input current, pulldown resistor Output high voltage Output high voltage Output low voltage Output low voltage DC Injection Current Per Pin(3) Capacitance
1
IINpu
41
111
A
D3.17
IINpd
36
106
A
D3.18
VOH VOHDDR VOL VOLDDR ICS
2.4 1.7 -- -- -1.0 --
-- -- 0.4 0.4 1.0 15
V V V V mA pF
D3.19 D3.20 D3.21 D3.22 D3.23 D3.24
Vin = 0V, f = 1 MHz
Cin
NOTES: Leakage current is measured with output drivers disabled and pull-up/pull-downs inactive. 2 See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin as listed in Table 52. 3 All injection current is transferred to VDD_IO/VDD_IO_MEM. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation.
Table 4. Drive Capability of MPC5200B Output Pins
Driver Type DRV4 DRV8 DRV8_OD DRV16_MEM DRV16_MEM PCI Supply Voltage VDD_IO = 3.3V VDD_IO = 3.3V VDD_IO = 3.3V VDD_IO_MEM = 3.3V VDD_IO_MEM = 2.5V VDD_IO = 3.3V IOH 4 8 16 16 16 IOL 4 8 8 16 16 16 Unit mA mA mA mA mA mA SpecID D3.25 D3.26 D3.27 D3.28 D3.29 D3.30
MPC5200B Data Sheet, Rev. 1 8 Freescale Semiconductor
Electrical and Thermal Characteristics
3.1.4
Electrostatic Discharge
CAUTION This device contains circuitry that protects against damage due to high-static voltage or electrical fields. However, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages. Operational reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (i.e., either GND or VCC ). Table 7 gives package thermal characteristics for this device.
Table 5. ESD and Latch-Up Protection Characteristics
Sym VHBM VMM VCDM ILAT
Rating Human Body Model (HBM)--JEDEC JESD22-A114-B Machine Model (MM)--JEDEC JESD22-A115 Charge Device Model (CDM)--JEDEC JESD22-C101 Latch-up Current at positive negative TA=85oC
Min 2000 200 500 +100 -100 +200 -200
Max -- -- -- --
Unit V V V mA
SpecID D4.1 D4.2 D4.3 D4.4
ILAT
Latch-up Current at TA=27oC positive negative
D4.5 -- mA
3.1.5
Power Dissipation
Power dissipation of the MPC5200B is caused by 3 different components: the dissipation of the internal or core digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and CORE_PLL_AVDD) and the dissipation of the IO logic (supplied by VDD_IO_MEM and VDD_IO). Table 6 details typical measured core and analog power dissipation figures for a range of operating modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated by the user for each application case using the following formula:
P IO = P IOint +
N x C x VDD_IO
M
2
xf
Eqn. 1
where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the MPC5200B processor must not exceed the value, which would cause the maximum junction temperature to be exceeded.
P total = P core + P analog + P IO Eqn. 2
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 9
Electrical and Thermal Characteristics
Table 6. Power Dissipation
Core Power Supply (VDD_CORE) SYS_XTAL/XLB/PCI/IPB/CORE (MHz) SpecID Mode 33/66/33/33/264 Typ Operational Doze Nap Sleep Deep-Sleep 727.5 -- -- -- 52.5 33/132/66/132/396 Typ 1080 600 225 225 52.5 mW mW mW mW mW
(1),(2) (1),(3) (1),(4) (1),(5) (1),(6)
Unit
Notes
D5.1 D5.2 D5.3 D5.4 D5.5
PLL Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD) Mode Typical Typ 2 Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO8) Mode Typical Typ 33 Unit mW Notes
(9)
Unit mW
Notes
(7)
D5.6
D5.7
NOTES: 1 Typical core power is measured at VDD_CORE = 1.5 V, Tj = 25 C 2 Operational power is measured while running an entirely cache-resident program with floating-point multiplication instructions in parallel with a continuous PCI transaction via BestComm. 3 Doze power is measured with the e300 core in Doze mode, the system oscillator, System PLL and Core PLL are active, all other system modules are inactive 4 Nap power is measured with the e300 core in Nap mode, the system oscillator, System PLL and Core PLL are active, all other system modules are inactive 5 Sleep power is measured with the e300 core in Sleep mode, the system oscillator, System PLL and Core PLL are active, all other system modules are inactive 6 Deep-Sleep power is measured with the e300 core in Sleep mode, the system oscillator, System PLL, Core PLL and all other system modules are inactive 7 Typical PLL power is measured at SYS_PLL_AVDD = CORE_PLL_AVDD = 1.5 V, Tj = 25 C 8 IO power figures given in the table represent the worst case scenario. For the VDD_MEM_IO rail connected to 2.5V the IO power is expected to be lower and bounded by the worst case with VDD_MEM_IO connected to 3.3V. 9 Unloaded typical I/O power is measured in Deep-Sleep mode at VDD_IO = VDD_MEM_IO SDR= 3.3 V, Tj = 25 C
MPC5200B Data Sheet, Rev. 1 10 Freescale Semiconductor
Electrical and Thermal Characteristics
3.1.6
Thermal Characteristics
Table 7. Thermal Resistance Data
Rating Board Layers Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) Sym RJA RJMA RJMA RJMA RJB RJC Natural Convection JT Value 30 22 24 19 14 8 2 Unit C/W C/W C/W C/W C/W C/W C/W Notes
(1),(2)
SpecID D6.1 D6.2 D6.3 D6.4 D6.5 D6.6 D6.7
Junction to Ambient Natural Convection Junction to Ambient Natural Convection Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board Junction to Case Junction to Package Top
(1),(3)
(1),(3)
(1),(3)
(4) (5) (6)
NOTES: 1 Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2 Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3 Per JEDEC JESD51-6 with the board horizontal. 4 Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5 Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6 Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
3.1.6.1
Heat Dissipation
TJ = TA +(R JA x PD ) Eqn. 3
An estimation of the chip-junction temperature, TJ, can be obtained from the following equation:
where: TA = ambient temperature for the package (C) R JA = junction to ambient thermal resistance (C/W) PD = power dissipation in package (W) The junction to ambient thermal resistance is an industry standard value, which provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board, and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is correct depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 11
Electrical and Thermal Characteristics
Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance:
R JA = R JC +R CA Eqn. 4
where: R JA = junction to ambient thermal resistance (C/W) R JC = junction to case thermal resistance (C/W) R CA = case to ambient thermal resistance (C/W) R JC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, R CA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. A more accurate thermal model can be constructed from the junction to board thermal resistance and the junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used for either hand estimations or for a computational fluid dynamics (CFD) thermal model. To determine the junction temperature of the device in the application after prototypes are available, the Thermal Characterization Parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation:
TJ = TT +( JT x PD ) Eqn. 5
where: TT = thermocouple temperature on top of package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned, so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over approximately one mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
3.2
Oscillator and PLL Electrical Characteristics
The MPC5200B System requires a system-level clock input SYS_XTAL. This clock input may be driven directly from an external oscillator or with a crystal using the internal oscillator. There is a separate oscillator for the independent Real-Time Clock (RTC) system.
MPC5200B Data Sheet, Rev. 1 12 Freescale Semiconductor
Electrical and Thermal Characteristics
The MPC5200B clock generation uses two phase locked loop (PLL) blocks. * The system PLL (SYS_PLL) takes an external reference frequency and generates the internal system clock. The system clock frequency is determined by the external reference frequency and the settings of the SYS_PLL configuration. * The e300 core PLL (CORE_PLL) generates a master clock for all of the CPU circuitry. The e300 core clock frequency is determined by the system clock frequency and the settings of the CORE_PLL configuration.
3.2.1
System Oscillator Electrical Characteristics
Table 8. System Oscillator Electrical Characteristics
Characteristic Sym fsys_xtal tup_osc Notes Min 15.6 -- Typical 33.3 -- Max 35.0 10 Unit MHz ms SpecID O1.1 O1.2
SYS_XTAL frequency Oscillator start-up time
3.2.2
RTC Oscillator Electrical Characteristics
Table 9. RTC Oscillator Electrical Characteristics
Characteristic Sym frtc_xtal Notes Min -- Typical 32.768 Max -- Unit kHz SpecID O2.1
RTC_XTAL frequency
3.2.3
System PLL Electrical Characteristics
Table 10. System PLL Specifications
Characteristic Sym fsys_xtal tsys_xtal tjitter fVCOsys tlock Notes
(1) (1) (2) (1) (3)
Min 15.6 66.6 -- 250 --
Typical 33.3 30.0 -- 533 --
Max 35.0 28.5 150 800 100
Unit MHz ns ps MHz s
SpecID O3.1 O3.2 O3.3 O3.4 O3.5
SYS_XTAL frequency SYS_XTAL cycle time SYS_XTAL clock input jitter System VCO frequency System PLL relock time
NOTES: 1 The SYS_XTAL frequency and PLL Configuration bits must be chosen such that the resulting system frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. 2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter will be passed into and through the PLL to the internal clock circuitry. 3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLKare reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 13
Electrical and Thermal Characteristics
3.2.4
e300 Core PLL Electrical Characteristics
The internal clocking of the e300 core is generated from and synchronized to the system clock by means of a voltage-controlled core PLL.
Table 11. e300 PLL Specifications
Characteristic e300 frequency e300 cycle time e300 VCO frequency e300 input clock frequency e300 input clock cycle time e300 input clock jitter e300 PLL relock time Sym fcore tcore fVCOcore fXLB_CLK tXLB_CLK tjitter tlock
(2) (3)
Notes
(1) (1) (1)
Min 50 2.85 400 25 2.73 -- --
Typical -- -- -- -- -- -- --
Max 550 40.0 1200 367 50.0 150 100
Unit MHz ns MHz MHz ns ps s
SpecID O4.1 O4.2 O4.3 O4.4 O4.5 O4.6 O4.7
NOTES: 1 The XLB_CLK frequency and e300 PLL Configuration bits must be chosen such that the resulting system frequencies, CPU (core) frequency, and e300 PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies in Table 12. 2 This represents total input jitter - short term and long term combined - and is guaranteed by design. Two different types of jitter can exist on the input to CORE_SYSCLK, systemic and true random jitter. True random jitter is rejected. Systemic jitter will be passed into and through the PLL to the internal clock circuitry. 3 Relock time is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for the PLL lock after a stable VDD and CORE_SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep modes.
3.3
* * * * * * * * *
AC Electrical Characteristics
AC Operating Frequency Data Clock AC Specifications Resets External Interrupts SDRAM PCI Local Plus Bus ATA Ethernet * * * * * * * * USB SPI MSCAN I2C J1850 PSC GPIOs and Timers IEEE 1149.1 (JTAG) AC Specifications
Hyperlinks to the indicated timing specification sections are provided below.
MPC5200B Data Sheet, Rev. 1 14 Freescale Semiconductor
Electrical and Thermal Characteristics
AC Test Timing Conditions: Unless otherwise noted, all test conditions are as follows: * TA = -40 to 85 oC * Tj = -40 to 115 oC * VDD_CORE = 1.42 to 1.58 V VDD_IO = 3.0 to 3.6 V * Input conditions: All Inputs: tr, tf <= 1 ns * Output Loading: All Outputs: 50 pF
3.3.1
AC Operating Frequency Data
Table 12. Clock Frequencies
Min 1 2 3 4 5 6 e300 Processor Core SDRAM Clock XL Bus Clock IP Bus Clock PCI / Local Plus Bus Clock PLL Input Range -- -- -- -- -- 15.6 Max 400 133 133 133 66 35 Units MHz MHz MHz MHz MHz MHz SpecID A1.1 A1.2 A1.3 A1.4 A1.5 A1.6
Table 12 provides the operating frequency information for the MPC5200B.
3.3.2
Clock AC Specifications
t CYCLE t DUTY t DUTY t RISE CV IH
SYSCLK
t FALL
VM
VM
VM
CV IL
Figure 2. Timing Diagram--SYS_XTAL_IN Table 13. SYS_XTAL_IN Timing
Sym t CYCLE t RISE SYS_XTAL_IN cycle time. SYS_XTAL_IN rise time. Description
(1)
Min 28.6 --
Max 64.1 5.0
Units ns ns
SpecID A2.1 A2.2
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 15
Electrical and Thermal Characteristics
Table 13. SYS_XTAL_IN Timing (continued)
Sym t FALL t DUTY CV IH CV IL
1
Description SYS_XTAL_IN fall time. SYS_XTAL_IN duty cycle (measured at V M ). SYS_XTAL_IN input voltage high SYS_XTAL_IN input voltage low
(2)
Min -- 40.0 2.0 --
Max 5.0 60.0 -- 0.8
Units ns % V V
SpecID A2.3 A2.4 A2.5 A2.6
NOTES: CAUTION--The SYS_XTAL_IN frequency and system PLL_CFG[0-6] settings must be chosen such that the resulting system frequencies do not exceed their respective maximum or minimum operating frequencies. See the MPC5200B User Manual [1]. 2 SYS_XTAL_IN duty cycle is measured at V . M
3.3.3
Resets
The MPC5200B has three reset pins: * PORRESET - Power on Reset * HRESET - Hard Reset * SRESET - Software Reset These signals are asynchronous I/O signals and can be asserted at any time. The input side uses a Schmitt trigger and requires the same input characteristics as other MPC5200B inputs, as specified in the DC Electrical Specifications section. Table 14 specifies the pulse widths of the Reset inputs.
Table 14. Reset Pulse Width
Name PORRESET HRESET SRESET Description Power On Reset Hardware Reset Software Reset Min Pulse Width tVDD_stable+tup_osc+tlock 4 clock cycles 4 clock cycles Max Pulse Width -- -- -- Reference Clock SYS_XTAL_IN SYS_XTAL_IN SYS_XTAL_IN SpecID A3.1 A3.2 A3.3
NOTES: 1. For PORRESET the value of the minimum pulse width reflects the power on sequence. If PORRESET is asserted afterwards its minimum pulse width equals the minimum given for HRESET related to the same reference clock. 2. The tVDD_stable describes the time which is needed to get all power supplies stable. 3. For tlock, refer to the Oscillator/PLL section of this specification for further details. 4. For tup_osc, refer to the Oscillator/PLL section of this specification for further details. 5. Following the deassertion of PORRESET, HRESET and SRESET remain low for 4096 reference clock cycles. 6. The deassertion of HRESET for at least the minimum pulse width forces the internal resets to be active for an additional 4096 clock cycles.
NOTE As long as VDD is not stable the HRESET output is not stable.
MPC5200B Data Sheet, Rev. 1 16 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 15. Reset Rise / Fall Timing
Description PORRESET fall time PORRESET rise time HRESET fall time HRESET rise time SRESET fall time SRESET rise time Min -- -- -- -- -- -- Max 1 1 1 1 1 1 Unit ms ms ms ms ms ms SpecID A3.4 A3.5 A3.6 A3.7 A3.8 A3.9
NOTES: Make sure that the PORRESET does not carry any glitches. The MPC5200B has no filter to prevent them from getting into the chip. HRESET and SRESET must have a monotonous rise time. The assertion of HRESET becomes active at Power on Reset without any SYS_XTAL clock.
For additional information, see the MPC5200B User Manual [1].
3.3.3.1
Reset Configuration Word
During reset (HRESET and PORRESET) the Reset Configuration Word is latched in the related Reset Configuration Word Register with each rising edge of the SYS_XTAL signal. If both resets (HRESET and PORRESET) are inactive (high), the contents of this register will be locked immediately with the SYS_XTAL clock (see Figure 3).
4096 clocks
SYS_XTAL PORRESET HRESET RST_CFG_WRD
sample sample sample sample sample sample sample sample sample sample LOCK
Figure 3. Reset Configuration Word Locking
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 17
Electrical and Thermal Characteristics
NOTE Beware of changing the values on the pins of the reset configuration word after the deassertion of PORRESET. This may cause problems because it may change the internal clock ratios and so extend the PLL locking process.
3.3.4
External Interrupts
The MPC5200B provides three different kinds of external interrupts: * Four IRQ interrupts * Eight GPIO interrupts with simple interrupt capability (not available in power-down mode) * Eight WakeUp interrupts (special GPIO pins) The propagation of these three kinds of interrupts to the core is shown in the following graphic:
IRQ0 8 GPIOs 8 GPIOs IRQ1 IRQ2 IRQ3
PIs 8 8 cint
Encoder
CORE_CINT CORE_INT
GPIO Std
int
GPIO WakeUp Grouper Encoder
e300 Core
Main Interrupt Controller Notes: 1. PIs = Programmable Inputs 2. Grouper and Encoder functions imply programmability in software Figure 4. External Interrupt Scheme
Due to synchronization, prioritization, and mapping of external interrupt sources, the propagation of external interrupts to the core processor is delayed by several IP_CLK clock cycles. The following table specifies the interrupt latencies in IP_CLK cycles. The IP_CLK frequency is programmable in the Clock Distribution Module (see Note Table 16).
Table 16. External Interrupt Latencies
Interrupt Type Interrupt Requests Pin Name IRQ0 IRQ0 IRQ1 IRQ2
IRQ3
Clock Cycles 10 10 10 10 10
Reference Clock IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK
Core Interrupt critical (cint) normal (int) normal (int) normal (int) normal (int)
SpecID A4.1 A4.2 A4.3 A4.4 A4.5
MPC5200B Data Sheet, Rev. 1 18 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 16. External Interrupt Latencies (continued)
Interrupt Type Standard GPIO Interrupts Pin Name GPIO_PSC3_4 GPIO_PSC3_5 GPIO_PSC3_8 GPIO_USB_9 GPIO_ETHI_4 GPIO_ETHI_5 GPIO_ETHI_6 GPIO_ETHI_7 GPIO WakeUp Interrupts GPIO_PSC1_4 GPIO_PSC2_4 GPIO_PSC3_9 GPIO_ETHI_8 GPIO_IRDA_0 DGP_IN0 DGP_IN1 Clock Cycles 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 Reference Clock IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK IP_CLK Core Interrupt normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) normal (int) SpecID A4.6 A4.7 A4.8 A4.9 A4.10 A4.11 A4.12 A4.13 A4.15 A4.16 A4.17 A4.18 A4.19 A4.20 A4.21
NOTES: 1) The frequency of IP_CLK depends on register settings in Clock Distribution Module. See the MPC5200B User Manual [1]. 2) The interrupt latency descriptions in the table above are related to non competitive, non masked but enabled external interrupt sources. Take care of interrupt prioritization which may increase the latencies.
Since all external interrupt signals are synchronized into the internal processor bus clock domain, each of these signals has to exceed a minimum pulse width of more than one IP_CLK cycle.
Table 17. Minimum Pulse Width for External Interrupts to be Recognized
Name All external interrupts (IRQs, GPIOs) Min Pulse Width > 1 clock cycle Max Pulse Width -- Reference Clock IP_CLK SpecID A4.22
NOTES: 1) The frequency of the IP_CLK depends on the register settings in Clock Distribution Module. See the MPC5200B User Manual [1] for further information. 2) If the same interrupt occurs a second time while its interrupt service routine has not cleared the former one, the second interrupt will not be recognized at all.
Besides synchronization, prioritization, and mapping the latency of an external interrupt to the start of its associated interrupt service routine also depends on the following conditions: To get a minimum interrupt service response time, it is recommended to enable the instruction cache and set up the maximum core clock, XL bus, and IP bus frequencies (depending on board design and programming). In addition, it is advisable to execute an interrupt handler, which has been implemented in assembly code.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 19
Electrical and Thermal Characteristics
3.3.5
3.3.5.1
Sym tmem_clk tvalid thold DMvalid DMhold
SDRAM
Memory Interface Timing-Standard SDRAM Read Command
Table 18. Standard SDRAM Memory Read Timing
Description MEM_CLK period Control Signals, Address and MBA Valid after rising edge of MEM_CLK Control Signals, Address and MBA Hold after rising edge of MEM_CLK DQM valid after rising edge of MEM_CLK DQM hold after rising edge of MEM_CLK Min 7.5 -- tmem_clk*0.5 -- tmem_clk*0.25-0.7 -- 0.2 Max -- tmem_clk*0.5+0.4 -- tmem_clk*0.25+0.4 -- 0.3 -- Units ns ns ns ns ns ns ns SpecID A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 A5.7
datasetup MDQ setup to rising edge of MEM_CLK datahold MDQ hold after rising edge of MEM_CLK
MEM_CLK
tvalid thold
Control Signals
Active
NOP
READ
NOP
DMhold
NOP
NOP
NOP
NOP
DMvalid
DQM (Data Mask)
datasetup datahold
MDQ (Data)
tvalid thold
MA (Address)
tvalid
Row
thold
Column
MBA (Bank Selects) NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure 5. Timing Diagram--Standard SDRAM Memory Read Timing
3.3.5.2
Memory Interface Timing-Standard SDRAM Write Command
In Standard SDRAM, all signals are activated on the MEM_CLK from the Memory Controller and captured on the MEM_CLK clock at the memory device.
MPC5200B Data Sheet, Rev. 1 20 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 19. Standard SDRAM Write Timing
Sym tmem_clk tvalid thold DMvalid DMhold datavalid datahold Description MEM_CLK period Control Signals, Address and MBA Valid after rising edge of MEM_CLK Control Signals, Address and MBA Hold after rising edge of MEM_CLK DQM valid after rising edge of MEM_CLK DQM hold after rising edge of Mem_clk MDQ valid after rising edge of MEM_CLK MDQ hold after rising edge of MEM_CLK Min 7.5 -- tmem_clk*0.5 -- tmem_clk*0.25-0.7 -- tmem_clk*0.75-0.7 Max -- tmem_clk*0.5+0.4 -- tmem_clk*0.25+0.4 -- tmem_clk*0.75+0.4 -- Units ns ns ns ns ns ns ns SpecID A5.8 A5.9 A5.10 A5.11 A5.12 A5.13 A5.14
MEM_CLK
tvalid thold
Control Signals
Active
DMvalid
NOP
WRITE
NOP
DMhold
NOP
NOP
NOP
NOP
DQM (Data Mask)
datavalid datahold
MDQ (Data)
tvalid thold
MA (Address)
tvalid
Row
thold
Column
MBA (Bank Selects) NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure 6. Timing Diagram--Standard SDRAM Memory Write Timing
3.3.5.3
Memory Interface Timing-DDR SDRAM Read Command
The SDRAM Memory Controller uses a 1/4 period delayed MDQS strobe to capture the MDQ data. The 1/4 period delay value is calculated automatically by hardware.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 21
Electrical and Thermal Characteristics
Table 20. DDR SDRAM Memory Read Timing
Sym tmem_clk tvalid thold datasetup datahold Description MEM_CLK period Control Signals, Address and MBA valid after rising edge of MEM_CLK Control Signals, Address and MBA hold after rising edge of MEM_CLK Setup time relative to MDQS Hold time relative to MDQS Min 7.5 -- tmem_clk*0.5 -- Max -- tmem_clk*0.5+0.4 -- 0.4 -- Units ns ns ns ns ns SpecID A5.15 A5.16 A5.17 A5.18 A5.19
MPC5200B Data Sheet, Rev. 1 22 Freescale Semiconductor
Electrical and Thermal Characteristics
MEM_CLK
MEM_CLK
tvalid thold
Control Signals
Active
NOP
READ
NOP
NOP
NOP
NOP
NOP
MDQS (Data Strobe)
tdata_valid_min tdata_valid_max
MDQ (Data)
tdata_sample_min tdata_sample_max
Sample position A
Read Data Sample Window
MDQS (Data Strobe)
tdata_valid_min tdata_valid_max
MDQ (Data)
0.5 * tMEM_CLK
tdata_sample_min tdata_sample_max
Sample position B
Read Data Sample Window
tvalid
thold
MA (Address)
tvalid
Row
thold
Column
MBA (Bank Selects)
Sample position A: data are sampled on the expected edge of MEM_CLK, the MDQS signal indicate the valid data Sample position B: data are sampled on a later edge of MEM_CLK, SDRAM controller is waiting for the vaild MDQS signal NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure 7. Timing Diagram--DDR SDRAM Memory Read Timing
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 23
Electrical and Thermal Characteristics
3.3.5.4
Sym tmem_clk tDQSS datavalid datahold
Memory Interface Timing-DDR SDRAM Write Command
Table 21. DDR SDRAM Memory Write Timing
Description MEM_CLK period Delay from write command to first rising edge of MDQS MDQ valid before rising edge of MDQS MDQ valid after rising edge of MDQS Min 7.5 -- TBD TBD Max -- tmem_clk+0.4 Units ns ns ns ns SpecID A5.20 A5.21 A5.22 A5.23
MEM_CLK
MEM_CLK
Control Signals
Write
Write
Write
Write
MDQS (Data Strobe)
tDQSS
MDQ (Data)
NOTE: Control Signals signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
Figure 8. DDR SDRAM Memory Write Timing
3.3.6
PCI
The PCI interface on the MPC5200B is designed to PCI Version 2.2 and supports 33-MHz and 66-MHz PCI operations. See the PCI Local Bus Specification [4]; the component section specifies the electrical and timing parameters for PCI components with the intent that components connect directly together whether on the planar or an expansion board, without any external buffers or other "glue logic." Parameters apply at the package pins, not at expansion board edge connectors. The MPC5200B is always the source of the PCI CLK. The clock waveform must be delivered to each 33-MHz or 66-MHz PCI component in the system. Figure 9 shows the clock waveform and required measurement points for 3.3 V signaling environments. Table 22 summarizes the clock specifications.
MPC5200B Data Sheet, Rev. 1 24 Freescale Semiconductor
Electrical and Thermal Characteristics
t cyc t high 0.6Vcc t low 0.4Vcc, p-to-p (minimum)
0.5Vcc 0.4Vcc PCI CLK 0.3Vcc
0.2Vcc Figure 9. PCI CLK Waveform
Table 22. PCI CLK Specifications
66 MHz Sym tcyc thigh t low Description Min PCI CLK Cycle Time PCI CLK High Time PCI CLK Low Time PCI CLK Slew Rate 15 6 6 1.5 4 Max 30 Min 30 11 11 1 4 Max ns ns ns V/ns
(2) (1),(3)
33 MHz Units Notes SpecID A6.1 A6.2 A6.3 A6.4
NOTES: 1. In general, all 66-MHz PCI components must work with any clock frequency up to 66 MHz. CLK requirements vary depending upon whether the clock frequency is above 33 MHz. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 9. 3. The minimum clock period must not be violated for any single clock cycle, i.e., accounting for all system jitter.
Table 23. PCI Timing Parameters
66 MHz Sym tval Description Min CLK to Signal Valid Delay - bused signals 2 2 2 14 3 5 0 7 10,12 0 Max 6 6 Min 2 2 2 28 Max 11 12 ns ns ns ns ns ns ns
(1),(2),(3)
33 MHz Units Notes SpecID A6.5 A6.6 A6.7 A6.8 A6.9 A6.10 A6.11
tval(ptp) CLK to Signal Valid Delay - point to point t on t off t su Float to Active Delay Active to Float Delay Input Setup Time to CLK - bused signals
(1),(2),(3)
(1) (1) (3),(4)
t su(ptp) Input Setup Time to CLK - point to point th Input Hold Time from CLK
(3),(4)
(4)
NOTES: 1. See the timing measurement conditions in the PCI Local Bus Specification [4]. It is important that all driven signal transitions drive to their Voh or Vol level within one Tcyc. 2. Minimum times are measured at the package pin with the load circuit, and maximum times are measured with the load circuit as shown in the PCI Local Bus Specification [4].
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 25
Electrical and Thermal Characteristics 3. REQ# and GNT# are point-to-point signals and have different input setup times than do bused signals. GNT# and REQ# have a setup of 5 ns at 66 MHz. All other signals are bused. 4. See the timing measurement conditions in the PCI Local Bus Specification [4].
For Measurement and Test Conditions, see the PCI Local Bus Specification [4].
3.3.7
Local Plus Bus
The Local Plus Bus is the external bus interface of the MPC5200B. A maximum of eight configurable chip selects (CS) are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz. Definition of Acronyms and Terms: WS = Wait State DC = Dead Cycle LB = Long Burst DS = Data Size in Bytes tPCIck = PCI clock period tIPBIck = IPBI clock period
tPCIck
PCI CLK
tIPBIck
IPBI CLK Figure 10. Timing Diagram--IPBI and PCI clock (example ratio: 4:1)
3.3.7.1
Sym t CSA t CSN t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
Non-MUXed Mode
Table 24. Non-MUXed Mode Timing
Description PCI CLK to CS assertion PCI CLK to CS negation CS pulse width ADDR valid before CS assertion ADDR hold after CS negation OE assertion before CS assertion OE negation before CS negation RW valid before CS assertion RW hold after CS negation DATA output valid before CS assertion DATA output hold after CS negation DATA input setup before CS negation Min 4.6 2.9 (2+WS)*tPCIck tIPBIck tIPBIck tPCIck tIPBIck tIPBIck tIPBIck 8.5 Max 10.6 7.0 (2+WS)*tPCIck tPCIck 4.8 2.7 Units ns ns ns ns ns ns ns ns ns ns ns ns
(2) (1)
Notes SpecID A7.1 A7.2 A7.3 A7.4 A7.5 A7.6 A7.7 A7.8 A7.9 A7.10 A7.11 A7.12
MPC5200B Data Sheet, Rev. 1 26 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 24. Non-MUXed Mode Timing (continued)
Sym t11 t12 t13 t14 t15 t16 t17 t18 t19 Description DATA input hold after CS negation ACK assertion after CS assertion ACK negation after CS negation TS assertion before CS assertion TS pulse width TSIZ valid before CS assertion TSIZ hold after CS negation ACK change before PCI clock ACK change after PCI clock Min 0 tPCIck tPCIck tIPBIck tIPBIck Max (DC+1)*tPCIck tPCIck 6.9 tPCIck 2.0 4.4 Units ns ns ns ns ns ns ns ns ns Notes SpecID
(6) (3) (3) (4) (4) (5) (5) (1) (1)
A7.13 A7.14 A7.15 A7.16 A7.17 A7.18 A7.19 A7.20 A7.21
NOTES: 1. ACK can shorten the CS pulse width. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from 0 65535. 2. In Large Flash and MOST Graphics mode the shared PCI/ATA pins, used as address lines, are released at the same moment as the CS. This can cause the address to change before CS is deasserted. 3. ACK is input and can be used to shorten the CS pulse width. 4. Only available in Large Flash and MOST Graphics mode. 5. Only available in MOST Graphics mode. 6. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration happens the bus can be driven within 4 IPB clocks by an other modules.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 27
Electrical and Thermal Characteristics
PCI CLK
t1
CS[x] ADDR
t2
t3
t4
t5
OE
t6 t7
R/W
t8 t9
DATA (wr)
t10 t11
DATA (rd)
t19
ACK
t14 t15
t12 t18
t13
TS TSIZ[1:2]
t16
t17
Figure 11. Timing Diagram--Non-MUXed Mode
3.3.7.2
Sym t CSA t CSN t1 t2 t3 t4 t5 t6 t7
Burst Mode
Table 25. Burst Mode Timing
Description PCI CLK to CS assertion PCI CLK to CS negation CS pulse width ADDR valid before CS assertion ADDR hold after CS negation OE assertion before CS assertion OE negation before CS negation RW valid before CS assertion RW hold after CS negation Min 4.6 2.9 (1+WS+4LB*2*(32/DS))* tPCIck tIPBIck -0.7 tPCIck tPCIck Max 10.6 7.0 (1+WS+4LB*2*(32/DS)) *tPCIck tPCIck 4.8 2.7 ns ns ns ns ns ns A7.25 A7.26 A7.27 A7.28 A7.29 A7.30 Units Notes SpecID ns ns ns
(1),(2)
A7.22 A7.23 A7.24
MPC5200B Data Sheet, Rev. 1 28 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 25. Burst Mode Timing (continued)
Sym t8 t9 t10 t11 t12 t13 t14 t15 Description DATA setup before rising edge of PCI clock DATA hold after rising edge of PCI clock DATA hold after CS negation ACK assertion after CS assertion ACK negation before CS negation ACK pulse width CS assertion after TS assertion TS pulse width Min 3.6 0 0 4LB*2*(32/DS)*tPCIck tPCIck Max (DC+1)*tPCIck (WS+1)*tPCIck 7.0 4LB*2*(32/DS)*tPCIck 2.5 tPCIck Units Notes SpecID ns ns ns ns ns ns ns ns
(3) (2),(3) (4)
A7.31 A7.32 A7.33 A7.34 A7.35 A7.36 A7.37 A7.38
NOTES: 1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from 0 65535. 2. Example: Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a burst on the internal XLB is executed. => LB = 1 Data bus width is 8 bit. => DS = 8 => 41*2*(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line. Wait State is set to 10. => WS = 10 1+10+32 = 43 => CS is asserted for 43 PCI cycles. 3. ACK is output and indicates the burst. 4. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration happens the bus can be driven within 4 IPB clocks by an other modules.
PCI CLK CS[x] ADDR
t4
t1
t2
t3
t5 t7 t8
t10
OE
t6
R/W DATA (rd)
t9 t11 t12 t13
ACK
t14 t15
TS
Figure 12. Timing Diagram--Burst Mode
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 29
Electrical and Thermal Characteristics
3.3.7.3
MUXed Mode
Table 26. MUXed Mode Timing
Sym t CSA t CSN tALEA t1 t2 t3 t4 t5 t6 t7 tTSA t8 t9 tOEA tOEN t10 t11 t12 t13 t14 t15 t16 Description PCI CLK to CS assertion PCI CLK to CS negation PCI CLK to ALE assertion ALE assertion before Address, Bank, TSIZ assertion CS assertion before Address, Bank, TSIZ negation CS assertion before Data wr valid Data wr hold after CS negation Data rd setup before CS negation Data rd hold after CS negation ALE pulse width CS assertion after TS assertion TS pulse width CS pulse width OE assertion before CS assertion OE negation before CS negation RW assertion before ALE assertion RW negation after CS negation ACK assertion after CS assertion ACK negation after CS negation ALE negation to CS assertion ACK change before PCI clock ACK change after PCI clock Min 4.6 2.9 tIPBIck 8.5 0 (2+WS)*tPCIck tIPBIck tIPBIck Max 10.6 7.0 3.6 5.7 -1.2 -1.2 (DC+1)*tPCIck tPCIck 6.9 tPCIck (2+WS)*tPCIck 4.7 5.9 tPCIck tPCIck tPCIck 2.0 4.4 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(2) (2) (2) (2) (1),(3)
Notes
SpecID A7.39 A7.40 A7.41 A7.42 A7.43 A7.44 A7.45 A7.46 A7.47 A7.48 A7.49 A7.50 A7.51 A7.52 A7.53 A7.54 A7.55 A7.56 A7.57 A7.58 A7.59 A7.60
NOTES:S 1. ACK can shorten the CS pulse width. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from 0 65535. 2. ACK is input and can be used to shorten the CS pulse width. 3. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration happens the bus can be driven within 4 IPB clocks by an other modules.
MPC5200B Data Sheet, Rev. 1 30 Freescale Semiconductor
Electrical and Thermal Characteristics
PCI CLK
t1 t2 t4
AD[31,27] (wr) AD[30:28] (wr) AD[26:25] (wr) AD[24:0] (wr) AD[31:0] (rd)
t7 t14
Data TSIZ[0:2] bits Data
Bank[0:1] bits Address[7:31]
t3
Data Data
t5 t6
Data
ALE
Address latch
t8
TS
t9
CSx OE
t10 t11
R/W
t16
ACK
Address tenure
t12 t15 t13
Data tenure
Figure 13. Timing Diagram--MUXed Mode
3.3.8
ATA
The MPC5200B ATA Controller is completely software programmable. It can be programmed to operate with ATA protocols using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in nature. Signal relationships are based on specific fixed timing in terms of timing units (nanoseconds). ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification [5] and how to program an ATA Controller and ATA drive for different ATA protocols and their respective timing. See the MPC5200B User Manual [1]. The MPC5200B ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in PIO and Multiword DMA modes.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 31
Electrical and Thermal Characteristics
* *
Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup-time beyond that required by the ATA-4 specification. Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold-time beyond that required by the ATA-4 specification.
All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes in which the ATA Controller can communicate with the drive. Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency to provide adequate data transfer rates. Adequate data transfer rates are a function of the following: * The MPC5200B operating frequency (IP bus clock frequency) * Internal MPC5200B bus latencies * Other system load dependent variables The ATA clock is the same frequency as the IP bus clock in MPC5200B. See the MPC5200B User Manual [1]. NOTE All output timing numbers are specified for nominal 50 pF loads.
Table 27. PIO Mode Timing Specifications
Sym t0 t1 t2 t2i t3 t4 t5 t6 t9 tA tB PIO Timing Parameter Cycle Time Address valid to DIOR/DIOW setup DIOR/DIOW pulse width 16-bit 8-bit DIOR/DIOW recovery time DIOW data setup DIOW data hold DIOR data setup DIOR data hold DIOR/DIOW to address valid hold IORDY setup IORDY pulse width Min/Max (ns) min min min min min min min min min min max max Mode 0 (ns) 600 70 165 290 -- 60 30 50 5 20 35 1250 Mode 1 (ns) 383 50 125 290 -- 45 20 35 5 15 35 1250 Mode 2 (ns) 240 30 100 290 -- 30 15 20 5 10 35 1250 Mode 3 (ns) 180 30 80 80 70 30 10 20 5 10 35 1250 Mode 4 (ns) 120 25 70 70 25 20 10 20 5 10 35 1250 SpecID A8.1 A8.2 A8.3 A8.4 A8.5 A8.6 A8.7 A8.8 A8.9 A8.10 A8.11
MPC5200B Data Sheet, Rev. 1 32 Freescale Semiconductor
Electrical and Thermal Characteristics
CS[0]/CS[3]/DA[2:0] t2 DIOR/DIOW t1 t0 t9
t3 WDATA t5 RDATA
t4
t6
tA IORDY
tB
Figure 14. PIO Mode Timing Table 28. Multiword DMA Timing Specifications
Sym t0 tC tD tE tG tF tH tI tJ tKr tKw tLr tLw Multiword DMA Timing Parameters Cycle Time DMACK to DMARQ delay DIOR/DIOW pulse width (16-bit) DIOR data access DIOR/DIOW data setup DIOR data hold DIOW data hold DMACK to DIOR/DIOW setup DIOR/DIOW to DMACK hold DIOR negated pulse width DIOW negated pulse width DIOR to DMARQ delay DIOW to DMARQ delay Min/Max min max min max min min min min min min min max max Mode 0(ns) 480 -- 215 150 100 5 20 0 20 50 215 120 40 Mode 1(ns) 150 -- 80 60 30 5 15 0 5 50 50 40 40 Mode 2(ns) 120 -- 70 50 20 5 10 0 5 25 25 35 35 SpecID A8.12 A8.13 A8.14 A8.15 A8.16 A8.17 A8.18 A8.19 A8.20 A8.21 A8.22 A8.23 A8.24
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 33
Electrical and Thermal Characteristics
t0 DMARQ (Drive) tC DMACK (Host) tI DIOR DIOW (Host) tE RDATA (Drive) tF WDATA (Host) tG tH tD tK tJ tL
Figure 15. Multiword DMA Timing
NOTE The direction of signal assertion is towards the top of the page, and the direction of negation is towards the bottom of the page, irrespective of the electrical properties of the signal.
Table 29. Ultra DMA Timing Specification
MODE 0 (ns) Min t CYC t 2CYC 114 235 Max -- -- MODE 1 (ns) Min 75 156 Max -- -- MODE 2 (ns) Min 55 117 Max -- -- Cycle time allowing for asymmetry and clock variations from STROBE edge to STROBE edge Two-cycle time allowing for clock variations, from rising edge to next rising edge or from falling edge to next falling edge of STROBE. Data setup time at recipient. Data hold time at recipient. Data valid setup time at sender, to STROBE edge. Data valid hold time at sender, from STROBE edge. First STROBE time for drive to first negate DSTROBE from STOP during a data-in burst. Limited Interlock time. Interlock time with minimum. A8.26 A8.27
Sym
Comment
SpecID
t DS t DH t DVS t DVH t FS t LI t MLI
15 5 70 6 0 0 20
-- -- -- -- 230 150 --
10 5 48 6 0 0 20
-- -- -- -- 200 150 --
7 5 34 6 0 0 20
-- -- -- -- 170 150 --
A8.28 A8.29 A8.30 A8.31 A8.32 A8.33 A8.34
MPC5200B Data Sheet, Rev. 1 34 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 29. Ultra DMA Timing Specification (continued)
MODE 0 (ns) Min t UI t AZ t ZAH t ZAD t ENV t SR 0 -- 20 0 20 -- Max -- 10 -- -- 70 50 MODE 1 (ns) Min 0 -- 20 0 20 -- Max -- 10 -- -- 70 30 MODE 2 (ns) Min 0 -- 20 0 20 -- Max -- 10 -- -- 70 20 Unlimited interlock time. Maximum time allowed for output drivers to release from being asserted or negated Minimum delay time required for output drivers to assert or negate from released state Envelope time--from DMACK to STOP and HDMARDY during data out burst initiation. STROBE to DMARDY time, if DMARDY is negated before this long after STROBE edge, the recipient receives no more than one additional data word. Ready-to-Final STROBE time--no STROBE edges are sent this long after negation of DMARDY. Ready-to-Pause time--the time recipient waits to initiate pause after negating DMARDY. Pull-up time before allowing IORDY to be released. Minimum time drive waits before driving IORDY Setup and hold times for DMACK, before assertion or negation. Time from STROBE edge to negation of DMARQ or assertion of STOP, when sender terminates a burst. A8.35 A8.36 A8.37 A8.38 A8.39 A8.40
Sym
Comment
SpecID
t RFS t RP t IORDYZ t ZIORDY t ACK t SS
-- 160 -- 0 20 50
75 -- 20 -- -- --
-- 125 -- 0 20 50
60 -- 20 -- -- --
-- 100 -- 0 20 50
50 -- 20 -- -- --
A8.41 A8.42 A8.43 A8.44 A8.45 A8.46
NOTES: 1 t UI, t MLI, t LI indicate sender-to-recipient or recipient-to-sender interlocks. That is, one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. * t UI is an unlimited interlock that has no maximum time value. * t MLI is a limited time-out that has a defined minimum. * t LI is a limited time-out that has a defined maximum. 2 All timing parameters are measured at the connector of the drive to which the parameter applies. For example, the sender shall stop generating STROBE edges t RFS after negation of DMARDY. Both STROBE and DMARDY timing measurements are taken at the connector of the sender. Even though the sender stops generating STROBE edges, the receiver may receive additional STROBE edges due to propagation delays. All timing measurement switching points (low to high and high to low) are taken at 1.5 V.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 35
Electrical and Thermal Characteristics
DMARQ (device) t UI DMACK (device) t ACK STOP (host) t ACK HDMARDY (host) t ZIORDY DSTROBE (device) t AZ DD(0:15) t ACK DA0, DA1, DA2, CS[0:1]1 t DVS t DVH t ZAD t ENV t ENV t ZAD t FS t FS
Figure 16. Timing Diagram--Initiating an Ultra DMA Data In Burst
t 2CYC t CYC t CYC t 2CYC DSTROBE at device tDVH DD(0:15) at device DSTROBE at host tDH DD(0:15) at host tDS tDH tDS tDH tDVS tDVH tDVS tDVH
Figure 17. Timing Diagram--Sustained Ultra DMA Data In Burst
MPC5200B Data Sheet, Rev. 1 36 Freescale Semiconductor
Electrical and Thermal Characteristics
DMARQ (device) DMARQ (host) STOP (host) t SR HDMARDY (host) t RFS DSTROBE (device) DD[0:15] (device)
t RP
Figure 18. Timing Diagram--Host Pausing an Ultra DMA Data In Burst
DMARQ (device) DMACK (host) t LI STOP (host) tLI HDMARDY (host) t SS DSTROBE (device) t ZAH t AZ DD[0:15] DA0,DA1,DA2, CS[0:1] CRC t ACK t DVS t DVH t IORDYZ t ACK t LI t MLI t ACK
Figure 19. Timing Diagram--Drive Terminating Ultra DMA Data In Burst
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 37
Electrical and Thermal Characteristics DMARQ (device) t LI DMACK (host) t RP STOP (host)
t AZ
t MLI
t ZAH
t ACK
tACK
HDMARDY (host) t RFS DSTROBE (device) t LI t MLI t IORDYZ t DVS t DVH DD[0:15] CRC t ACK DA0,DA1,DA2, CS[0:1]
Figure 20. Timing Diagram--Host Terminating Ultra DMA Data In Burst
DMARQ (device) DMACK (host) tACK STOP (host) tZIORDY DDMARDY (host) tACK HSTROBE (device) tDVS tDVH DD[0:15] (host) tACK DA0,DA1,DA2, CS[0:1] tLI tUI tENV
tUI
Figure 21. Timing Diagram--Initiating an Ultra DMA Data Out Burst
MPC5200B Data Sheet, Rev. 1 38 Freescale Semiconductor
Electrical and Thermal Characteristics t 2CYC t CYC HSTROBE (host) t DVH DD[0:15] (host) HSTROBE (device) t DH DD[0:15] (device) t DS t DH t DS t DH t DVS t DVH t DVS t DVH t CYC t 2CYC
Figure 22. Timing Diagram--Sustained Ultra DMA Data Out Burst
t RP DMARQ (device) DMACK (host) STOP (host) t SR DDMARDY (device) t RFS HSTROBE
DD[0:15] (host)
Figure 23. Timing Diagram--Drive Pausing an Ultra DMA Data Out Burst
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 39
Electrical and Thermal Characteristics DMARQ (device) t LI DMACK (host) t SS STOP (host) t LI DDMARDY (device) tACK HSTROBE (host) t DVS DD[0:15] (host) DA0,DA1,DA2, CS[0:1] CRC t ACK t DVH t IORDYZ t LI t ACK t MLI
Figure 24. Timing Diagram--Host Terminating Ultra DMA Data Out Burst
DMARQ (device) DMACK (host) t LI STOP (host) t RP DDMARDY (device) t RFS HSTROBE (host) t DVS DD[0:15] (host) CRC t ACK t DVH t LI t MLI t ACK t IORDYZ t MLI t ACK
DA0,DA1,DA2, CS[0:1]
Figure 25. Timing Diagram--Drive Terminating Ultra DMA Data Out Burst
MPC5200B Data Sheet, Rev. 1 40 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 30. Timing Specification ata_isolation
Sym 1 2 Description ata_isolation setup time ata_isolation hold time Min 7 Max 19 Units IP Bus cycles IP Bus cycles SpecID A8.48 A8.49
DIOR
ATA_ISOLATION 1 2
Figure 26. Timing Diagram-ATA-ISOLATION
3.3.9
Ethernet
AC Test Timing Conditions: * Output Loading All Outputs: 25 pF
Table 31. MII Rx Signal Timing
Sym t1 t2 t3 t4 Description RXD[3:0], RX_DV, RX_ER to RX_CLK setup RX_CLK to RXD[3:0], RX_DV, RX_ER hold RX_CLK pulse width high RX_CLK pulse width low Min 10 10 35% 35% Max -- -- 65% 65% Unit ns ns RX_CLK RX_CLK Period(1) Period(1) SpecID A9.1 A9.2 A9.3 A9.4
NOTES: 1 RX_CLK shall have a frequency of 25% of data rate of the received signal. See the IEEE 802.3 Specification [6].
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 41
Electrical and Thermal Characteristics
t3
RX_CLK (Input)
t4
RXD[3:0] (inputs) RX_DV RX_ER
t1 t2
Figure 27. Ethernet Timing Diagram--MII Rx Signal Table 32. MII Tx Signal Timing
Sym t5 t6 t7 t8 Description TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER invalid TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid TX_CLK pulse width high TX_CLK pulse width low Min 5 -- 35% 35% Max -- 25 65% 65% Unit ns ns TX_CLK TX_CLK Period(1) Period(1) SpecID A9.5 A9.6 A9.7 A9.8
NOTES: 1 The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5 MHz. See the IEEE 802.3 Specification [6].
t7 TX_CLK (Input) t5 TXD[3:0] (Outputs) TX_EN TX_ER t6 t8
Figure 28. Ethernet Timing Diagram--MII Tx Signal Table 33. MII Async Signal Timing
Sym t9 Description CRS, COL minimum pulse width Min 1.5 Max -- Unit TX_CLK Period SpecID A9.9
MPC5200B Data Sheet, Rev. 1 42 Freescale Semiconductor
Electrical and Thermal Characteristics
CRS, COL t9 Figure 29. Ethernet Timing Diagram--MII Async Table 34. MII Serial Management Channel Signal Timing
Sym t10 t11 t12 t13 t14 t15 Description MDC falling edge to MDIO output delay MDIO (input) to MDC rising edge setup MDIO (input) to MDC rising edge hold MDC pulse width MDC pulse width MDC period(2) high(1) low(1) Min 0 10 10 160 160 400 Max 25 -- -- -- -- -- Unit ns ns ns ns ns ns SpecID A9.10 A9.11 A9.12 A9.13 A9.14 A9.15
NOTES: 1 MDC is generated by MPC5200B with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register is changed during operation. See the MPC5200B User Manual [1]. 2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by programming the FEC MII_SPEED control register. See the MPC5200B User Manual [1].
t13 MDC (Output) t14 t15 t10 MDIO (Output)
MDIO (Input)
t11
t12
Figure 30. Ethernet Timing Diagram--MII Serial Management
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 43
Electrical and Thermal Characteristics
3.3.10 USB
Table 35. Timing Specifications--USB Output Line
Sym 1 2 3 4 USB Bit width(1) Transceiver enable time Signal falling time Signal rising time Description Min 83.3 83.3 -- -- Max 667 667 7.9 7.9 Units ns ns ns ns SpecID A10.1 A10.2 A10.3 A10.4
NOTES: 1 Defined in the USB config register, (12 Mbit/s or 1.5 Mbit/s mode).
NOTE Output timing is specified at a nominal 50 pF load.
2 USB_OE
3 USB_TXN 1 USB_TXP 1 4
4
3
Figure 31. Timing Diagram--USB Output Line
MPC5200B Data Sheet, Rev. 1 44 Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.11 SPI
Table 36. Timing Specifications -- SPI Master Mode, Format 0 (CPHA = 0)
Sym 1 2 3 4 5 6 7 8 9 10 11
Cycle time Clock high or low time Slave select to clock delay Output Data valid after Slave Select (SS) Output Data valid after SCK Input Data setup time Input Data hold time Slave disable lag time Sequential transfer delay Clock falling time Clock rising time
Description
Min 4 2 15.0 -- -- 20.0 20.0 15.0 1 -- --
Max 1024 512 -- 20.0 20.0 -- -- -- -- 7.9 7.9
Units IP-Bus Cycle(1) IP-Bus Cycle ns ns ns ns ns ns IP-Bus Cycle(1)
(1)
SpecID A11.1 A11.2 A11.3 A11.4 A11.5 A11.6 A11.7 A11.8 A11.9 A11.10 A11.11
ns ns
NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
NOTE Output timing is specified at a nominal 50 pF load.
1 10 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 5 11
2
2 11
10
8
9
4 MOSI Output 6 MISO Input
6
7
7
Figure 32. Timing Diagram -- SPI Master Mode, Format 0 (CPHA = 0)
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 45
Electrical and Thermal Characteristics
Table 37. Timing Specifications -- SPI Slave Mode, Format 0 (CPHA = 0)
Sym 1 2 3 4 5 6 7 8 9 Cycle time Clock high or low time Slave select to clock delay Output Data valid after Slave Select (SS) Output Data valid after SCK Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay Description Min 4 2 15.0 -- -- 50.0 0.0 15.0 1 Max 1024 512 -- 50.0 50.0 -- -- -- -- Units IP-Bus Cycle
(1)
SpecID A11.12 A11.13 A11.14 A11.15 A11.16 A11.17 A11.18 A11.19
(1)
IP-Bus Cycle(1) ns ns ns ns ns ns IP-Bus Cycle
A11.20
NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
NOTE Output timing is specified at a nominal 50 pF load.
1
SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 6 MOSI Input 4 MISO Output
2
2
8
9
7
5
Figure 33. Timing Diagram -- SPI Slave Mode, Format 0 (CPHA = 0)
MPC5200B Data Sheet, Rev. 1 46 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 38. Timing Specifications -- SPI Master Mode, Format 1 (CPHA = 1)
Sym 1 2 3 4 5 6 7 8 9 10 Cycle time Clock high or low time Slave select to clock delay Output data valid Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay Clock falling time Clock rising time Description Min 4 2 15.0 -- 20.0 20.0 15.0 1 -- -- Max 1024 512 -- 20.0 -- -- -- -- 7.9 7.9 Units IP-Bus Cycle
(1)
SpecID A11.21
IP-Bus Cycle(1) A11.22 ns ns ns ns ns IP-Bus Cycle ns ns
(1)
A11.23 A11.24 A11.25 A11.26 A11.27 A11.28 A11.29 A11.30
NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
NOTE Output timing is specified at a nominal 50 pF load.
1 9 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 10
2
2 10
9
7
8
4 MOSI Output 5 MISO Input 6 Figure 34. Timing Diagram -- SPI Master Mode, Format 1 (CPHA = 1)
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 47
Electrical and Thermal Characteristics
Table 39. Timing Specifications -- SPI Slave Mode, Format 1 (CPHA = 1)
Sym 1 2 3 4 5 6 7 8 Cycle time Clock high or low time Slave select to clock delay Output data valid Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay Description Min 4 2 15.0 -- 50.0 0.0 15.0 1 Max 1024 512 -- 50.0 -- -- -- -- Units IP-Bus Cycle
(1)
SpecID A11.31 A11.32 A11.33 A11.34 A11.35 A11.36 A11.37
(1)
IP-Bus Cycle(1) ns ns ns ns ns IP-Bus Cycle
A11.38
NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
NOTE Output timing is specified at a nominal 50 pF load.
1
SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input
2
2
7
8
5 MOSI Input 4 MISO Output
6
Figure 35. Timing Diagram -- SPI Slave Mode, Format 1 (CPHA = 1)
3.3.12 MSCAN
The CAN functions are available as RX and TX pins at normal IO pads (I2C1+GPTimer or PSC2). There is no filter for the WakeUp dominant pulse. Any High-to-Low edge can cause WakeUp, if configured.
MPC5200B Data Sheet, Rev. 1 48 Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.13 I2C
Table 40. I2C Input Timing Specifications--SCL and SDA
Sym 1 2 4 6 7 8 9 Description Start condition hold time Clock low time Data hold time Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 2 8 0.0 4 0.0 2 2 Max -- -- -- -- -- -- -- Units IP-Bus Cycle(1) IP-Bus Cycle(1) SpecID A13.1 A13.2 A13.3 A13.4 A13.5
(1)
ns IP-Bus Cycle(1) ns IP-Bus Cycle
A13.6 A13.7
IP-Bus Cycle(1)
NOTES: 1 Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
Table 41. I2C Output Timing Specifications--SCL and SDA
Sym 1 (1) 2(1) 3(2) 4(1) 5(1) 6(1) 7(1) 8(1) 9(1) Description Start condition hold time Clock low time SCL/SDA rise time Data hold time SCL/SDA fall time Clock high time Data setup time Start condition setup time (for repeated start condition only) Stop condition setup time Min 6 10 -- 7 -- 10 2 20 10 Max -- -- 7.9 -- 7.9 -- -- -- -- Units IP-Bus Cycle(3) IP-Bus Cycle(3) ns IP-Bus Cycle(3) SpecID A13.8 A13.9 A13.10 A13.11 A13.12
ns
IP-Bus Cycle(3) A13.13 IP-Bus Cycle(3) A13.14 IP-Bus Cycle(3) A13.15 IP-Bus Cycle(3) A13.16
NOTES: 1 Programming IFDR with the maximum frequency (IFDR=0x20) results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the prescale and division values programmed in IFDR. 2 Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values 3 Inter Peripheral Clock is defined in the MPC5200B User Manual [1].
NOTE Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 49
Electrical and Thermal Characteristics
2 SCL 1 SDA 4
6
5
7
8
3
9
Figure 36. Timing Diagram--I2C Input/Output
3.3.14 J1850
See the MPC5200B User Manual [1].
3.3.15 PSC
3.3.15.1 Codec Mode (8,16,24 and 32-bit) / I2S Mode
Table 42. Timing Specifications--8,16, 24, and 32-bit CODEC / I2S Master Mode
Sym 1 2 3 4 5 6 7 8 Description Bit Clock cycle time, programmed in CCS register Clock duty cycle Bit Clock fall time Bit Clock rise time FrameSync valid after clock edge FrameSync invalid after clock edge Output Data valid after clock edge Input Data setup time Min 40.0 -- -- -- -- -- -- 6.0 Typ -- 50 -- -- -- -- -- -- Max -- -- 7.9 7.9 8.4 8.4 9.3 -- Units ns %(1) ns ns ns ns ns ns SpecID A15.1 A15.2 A15.3 A15.4 A15.5 A15.6 A15.7 A15.8
NOTES: 1 Bit Clock cycle time
NOTE Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 1 50 Freescale Semiconductor
Electrical and Thermal Characteristics
1
BitClk (CLKPOL=0) Output BitClk (CLKPOL=1) Output 5 FrameSync (SyncPol = 1) Output FrameSync (SyncPol = 0) Output 7 TxD Output
3 2 2 4
4
3
6
8 RxD Input Figure 37. Timing Diagram -- 8,16, 24, and 32-bit CODEC / I2S Master Mode Table 43. Timing Specifications -- 8,16, 24, and 32-bit CODEC / I2S Slave Mode
Sym 1 2 3 4 5 6 Bit Clock cycle time Clock duty cycle FrameSync setup time Output Data valid after clock edge Input Data setup time Input Data hold time Description Min 40.0 -- 1.0 -- 1.0 1.0 Typ -- 50 -- -- -- -- Max -- -- -- 14.0 -- -- Units ns %(1) ns ns ns ns SpecID A15.9 A15.10 A15.11 A15.12 A15.13 A15.14
NOTES: 1 Bit Clock cycle time
NOTE Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 51
Electrical and Thermal Characteristics
1
BitClk (CLKPOL=0) Input BitClk (CLKPOL=1) Input
2
2
3 FrameSync (SyncPol = 1) Input FrameSync (SyncPol = 0) Input 4 TxD Output 5 RxD Input 6 Figure 38. Timing Diagram -- 8,16, 24, and 32-bit CODEC / I2S Slave Mode
3.3.15.2 AC97 Mode
Table 44. Timing Specifications -- AC97 Mode
Sym 1 2 3 4 5 6 7 Bit Clock cycle time Clock pulse high time Clock pulse low time FrameSync valid after rising clock edge Output Data valid after rising clock edge Input Data setup time Input Data hold time Description Min -- -- -- -- -- 1.0 1.0 Typ 81.4 40.7 40.7 -- -- -- -- Max -- -- -- 13.0 14.0 -- -- Units ns ns ns ns ns ns ns SpecID A15.15 A15.16 A15.17 A15.18 A15.19 A15.20 A15.21
NOTE Output timing is specified at a nominal 50 pF load.
MPC5200B Data Sheet, Rev. 1 52 Freescale Semiconductor
Electrical and Thermal Characteristics
1
BitClk (CLKPOL=0) Input FrameSync (SyncPol = 1) Output Sdata_out Output
4
3
2
5
6 Sdata_in Input
7
Figure 39. Timing Diagram -- AC97 Mode
3.3.15.3 IrDA Mode
Table 45. Timing Specifications -- IrDA Transmit Line
Sym 1 2 3 4 Description Pulse high time, defined in the IrDA protocol definition Pulse low time, defined in the IrDA protocol definition Transmitter rising time Transmitter falling time Min 0.125 0.125 -- -- Max 10000 10000 7.9 7.9 Units s s ns ns SpecID A15.22 A15.23 A15.24 A15.25
NOTE Output timing is specified at a nominal 50 pF load.
3 IrDA_TX (SIR / FIR / MIR) 1 2
4
Figure 40. Timing Diagram -- IrDA Transmit Line
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 53
Electrical and Thermal Characteristics
3.3.15.4 SPI Mode
Table 46. Timing Specifications -- SPI Master Mode, Format 0 (CPHA = 0)
Sym 1 2 3 4 5 6 7 8 9 10 11 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay, programable in the PSC CCS register Output Data valid after Slave Select (SS) Output Data valid after SCK Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay, programable in the PSC CTUR / CTLR register Clock falling time Clock rising time Min 30.0 15.0 30.0 -- -- 6.0 1.0 -- 15.0 -- -- Max -- -- -- 8.9 8.9 -- -- 8.9 -- 7.9 7.9 Units ns ns ns ns ns ns ns ns ns ns ns SpecID A15.26 A15.27 A15.28 A15.29 A15.30 A15.31 A15.32 A15.33 A15.34 A15.35 A15.36
NOTE Output timing is specified at a nominal 50 pF load.
1 10 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 5 11
2
2 11
10
8
9
4 MOSI Output 6 MISO Input
6
7
7
Figure 41. Timing Diagram -- SPI Master Mode, Format 0 (CPHA = 0)
MPC5200B Data Sheet, Rev. 1 54 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 47. Timing Specifications -- SPI Slave Mode, Format 0 (CPHA = 0)
Sym 1 2 3 4 5 6 7 8 9 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay Input Data setup time Input Data hold time Output data valid after SS Output data valid after SCK Slave disable lag time Minimum Sequential Transfer delay = 2 * IP Bus clock cycle time Min 30.0 15.0 1.0 1.0 1.0 -- -- 0.0 30.0 Max -- -- -- -- -- 14.0 14.0 -- -- Units ns ns ns ns ns ns ns ns -- SpecID A15.37 A15.38 A15.39 A15.40 A15.41 A15.42 A15.43 A15.44 A15.45
NOTE Output timing is specified at a nominal 50 pF load.
1
SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input 4 MOSI Input 6 MISO Output
2
2
8
9
5
7
Figure 42. Timing Diagram -- SPI Slave Mode, Format 0 (CPHA = 0)
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 55
Electrical and Thermal Characteristics
Table 48. Timing Specifications -- SPI Master Mode, Format 1 (CPHA = 1)
Sym 1 2 3 4 5 6 7 8 9 10 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay, programable in the PSC CCS register Output data valid Input Data setup time Input Data hold time Slave disable lag time Sequential Transfer delay, programable in the PSC CTUR / CTLR register Clock falling time Clock rising time Min 30.0 15.0 30.0 -- 6.0 1.0 -- 15.0 -- -- Max -- -- -- 8.9 -- -- 8.9 -- 7.9 7.9 Units ns ns ns ns ns ns ns ns ns ns SpecID A15.46 A15.47 A15.48 A15.49 A15.50 A15.51 A15.52 A15.53 A15.54 A15.55
NOTE Output timing is specified at a nominal 50 pF load.
1 9 SCK (CLKPOL=0) Output SCK (CLKPOL=1) Output 3 SS Output 10
2
2 10
9
7
8
4 MOSI Output 5 MISO Input 6
Figure 43. Timing Diagram -- SPI Master Mode, Format 1 (CPHA = 1)
MPC5200B Data Sheet, Rev. 1 56 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 49. Timing Specifications -- SPI Slave Mode, Format 1 (CPHA = 1)
Sym 1 2 3 4 5 6 7 8 Description SCK cycle time, programable in the PSC CCS register SCK pulse width, 50% SCK duty cycle Slave select clock delay Output data valid Input Data setup time Input Data hold time Slave disable lag time Minimum Sequential Transfer delay = 2 * IP-Bus clock cycle time Min 30.0 15.0 0.0 -- 2.0 1.0 0.0 30.0 Max -- -- -- 14.0 -- -- -- -- Units ns ns ns ns ns ns ns ns SpecID A15.56 A15.57 A15.58 A15.59 A15.60 A15.61 A15.62 A15.63
NOTE Output timing is specified at a nominal 50 pF load.
1
SCK (CLKPOL=0) Input SCK (CLKPOL=1) Input 3 SS Input
2
2
7
8
5 MOSI Input 4 MISO Output
6
Figure 44. Timing Diagram -- SPI Slave Mode, Format 1 (CPHA = 1)
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 57
Electrical and Thermal Characteristics
3.3.16 GPIOs and Timers
3.3.16.1 General and Asynchronous Signals
The MPC5200B contains several sets if I/Os that do not require special setup, hold, or valid requirements. Most of these are asynchronous to the system clock. The following numbers are provided for test and validation purposes only, and they assume a 133 MHz internal bus frequency. Figure 45 shows the GPIO Timing Diagram. Table 50 gives the timing specifications.
Table 50. Asynchronous Signals
Sym tCK tIS tIH tDV tDH Clock Period Input Setup Input Hold Output Valid Output Hold Description Min 7.52 12 1 -- 1 Max -- -- -- 15.33 -- Units ns ns ns ns ns SpecID A16.1 A16.2 A16.3 A16.4 A16.5
tCK tDV Output tIS Input valid valid tIH tDH
Figure 45. Timing Diagram--Asynchronous Signals
MPC5200B Data Sheet, Rev. 1 58 Freescale Semiconductor
Electrical and Thermal Characteristics
3.3.17 IEEE 1149.1 (JTAG) AC Specifications
Table 51. JTAG Timing Specification
Sym -- 1 2 3 4 5 6 7 8 9 10 11 12 13 Characteristic TCK frequency of operation. TCK cycle time. TCK clock pulse width measured at 1.5V. TCK rise and fall times. TRST setup time to tck falling edge . TRST assert time. Input data setup time . Input data hold time(2) . valid(3). impedance(3).
(2) (1)
Min 0 40 1.08 0 10 5 5 15 0 0 5 1 0 0
Max 25 -- -- 3 -- -- -- -- 30 30 -- -- 15 15
Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
SpecID A17.1 A17.2 A17.3 A17.4 A17.5 A17.6 A17.7 A17.8 A17.9 A17.10 A17.11 A17.12 A17.13 A17.14
TCK to output data TCK to output high
TMS, TDI data setup time. TMS, TDI data hold time. TCK to TDO data valid. TCK to TDO high impedance.
NOTES: 1 TRST is an asynchronous signal. The setup time is for test purposes only. 2 Non-test, other than TDI and TMS, signal input timing with respect to TCK. 3 Non-test, other than TDO, signal output timing with respect to TCK.
1 2 TCK
VM VM
2
VM
3
3
VM = Midpoint Voltage Numbers shown reference Table 51.
Figure 46. Timing Diagram--JTAG Clock Input
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 59
Electrical and Thermal Characteristics
TCK 4 TRST 5
Numbers shown reference Table 51.
Figure 47. Timing Diagram--JTAG TRST
TCK 6 DATA INPUTS 8 DATA OUTPUTS 9 DATA OUTPUTS
Numbers shown reference Table 51.
OUTPUT DATA VALID
7
INPUT DATA VALID
Figure 48. Timing Diagram--JTAG Boundary Scan
TCK 10 TDI, TMS 12 TDO 13 TDO
Numbers shown reference Table 51.
OUTPUT DATA VALID
11
INPUT DATA VALID
Figure 49. Timing Diagram--Test Access Port
MPC5200B Data Sheet, Rev. 1 60 Freescale Semiconductor
Package Description
4
4.1
Package Description
Package Parameters
The MPC5200B uses a 27 mm x 27 mm TE-PBGA package. The package parameters are as provided in the following list: * Package outline: 27 mm x 27 mm * Interconnects: 272 * Pitch: 1.27 mm
4.2
Mechanical Dimensions
Figure 50 provides the mechanical dimensions, top surface, side profile, and pinout for the MPC5200B, 272 TE-PBGA package.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 61
Package Description
PIN A1 INDEX
D
C
4X
0.2 A
272X
0.2 A E E2 0.35 A
D2 B TOP VIEW (D1)
19X
0.2
M
ABC
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A. 4. PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. MILLIMETERS MIN MAX 2.05 2.65 0.50 0.70 0.50 0.70 1.05 1.25 0.60 0.90 27.00 BSC 24.13 REF 23.30 24.70 27.00 BSC 24.13 REF 23.30 24.70 1.27 BSC
e
Y W V U T R P N M L K J H G F E D C B A
19X
e
DIM A A1 A2 A3 b D D1 D2 E E1 E2 e
(E1)
4X
A1 A3 A2 A SIDE VIEW
272X
e /2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
b3 0.3
M M
BOTTOM VIEW
ABC A
0.15
CASE 1135A-01 ISSUE B DATE 10/15/1997
Figure 50. Mechanical Dimensions and Pinout Assignments for the MPC5200B, 272 TE-PBGA
MPC5200B Data Sheet, Rev. 1 62 Freescale Semiconductor
Package Description
4.3
Pinout Listings
Table 52. MPC5200B Pinout Listing
Name Alias Type Power Supply SDRAM Output Driver Type Input Type Pull-up/ down
See details in the MPC5200B User Manual [1].
MEM_CAS MEM_CLK_EN MEM_CS MEM_DQM[3:0] MEM_MA[12:0] MEM_MBA[1:0] MEM_MDQS[3:0] MEM_MDQ[31:0] MEM_CLK MEM_CLK MEM_RAS MEM_WE
CAS CLK_EN
I/O I/O I/O
VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO VDD_MEM_IO PCI
DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM DRV16_MEM
TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL
DQM MA MBA MDQS MDQ
I/O I/O I/O I/O I/O I/O I/O
RAS
I/O I/O
EXT_AD[31:0] PCI_CBE_0 PCI_CBE_1 PCI_CBE_2 PCI_CBE_3 PCI_CLOCK PCI_DEVSEL PCI_FRAME PCI_GNT PCI_IDSEL PCI_IRDY PCI_PAR PCI_PERR PCI_REQ PCI_RESET PCI_SERR PCI_STOP
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
PCI PCI PCI PCI PCI PCI PCI PCI DRV8 DRV8 PCI PCI PCI DRV8 PCI PCI PCI
PCI PCI PCI PCI PCI PCI PCI PCI TTL TTL PCI PCI PCI TTL PCI PCI PCI
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 63
Package Description
Table 52. MPC5200B Pinout Listing (continued)
Name PCI_TRDY Alias Type I/O Power Supply VDD_IO Local Plus LP_ACK LP_ALE LP_OE LP_RW LP_TS LP_CS0 LP_CS1 LP_CS2 LP_CS3 LP_CS4 LP_CS5 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ATA ATA_DACK ATA_DRQ ATA_INTRQ ATA_IOCHRDY ATA_IOR ATA_IOW ATA_ISOLATION I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO Ethernet ETH_0 ETH_1 ETH_2 ETH_3 ETH_4 ETH_5 ETH_6 ETH_7 TX, TX_EN RTS, TXD[0] USB_TXP, RTS, TXD[1] USB_PRTPWR, TXD[2] USB_SPEED, TXD[3] USB_SUPEND, TX_ER USB_OE, RTS, MDC TXN, MDIO I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 TTL TTL TTL TTL TTL TTL TTL TTL DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 TTL TTL TTL TTL TTL TTL TTL PULLDOWN PULLDOWN PULLUP DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 DRV8 TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL PULLUP Output Driver Type PCI Input Type PCI Pull-up/ down
MPC5200B Data Sheet, Rev. 1 64 Freescale Semiconductor
Package Description
Table 52. MPC5200B Pinout Listing (continued)
Name ETH_8 ETH_9 ETH_10 ETH_11 ETH_12 ETH_13 ETH_14 ETH_15 ETH_16 ETH_17 Alias RX_DV CD, RX_CLK CTS, COL TX_CLK RXD[0] USB_RXD, CTS, RXD[1] USB_RXP, UART_RX, RXD[2] USB_RXN, RX, RXD[3] USB_OVRCNT, CTS, RX_ER CD, CRS Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO IRDA PSC6_0 PSC6_1 PSC6_2 PSC6_3 IRDA_RX, RxD Frame, CTS IRDA_TX, TxD IR_USB_CLK,BitC lk, RTS I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO USB USB_0 USB_1 USB_2 USB_3 USB_4 USB_5 USB_6 USB_7 USB_8 USB_9 USB_OE USB_TXN USB_TXP USB_RXD USB_RXP USB_RXN USB_PRTPWR USB_SPEED USB_SUPEND USB_OVRCNT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO I2C I2C_0 I2C_1 I2C_2 SCL SDA SCL I/O I/O I/O VDD_IO VDD_IO VDD_IO DRV4 DRV4 DRV4 Schmitt Schmitt Schmitt DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL DRV4 DRV4 DRV4 DRV4 TTL TTL TTL Schmitt Output Driver Type DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 Input Type TTL Schmitt TTL Schmitt TTL TTL TTL TTL TTL TTL Pull-up/ down
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 65
Package Description
Table 52. MPC5200B Pinout Listing (continued)
Name I2C_3 Alias SDA Type I/O Power Supply VDD_IO PSC PSC1_0 PSC1_1 PSC1_2 PSC1_3 PSC1_4 PSC2_0 PSC2_1 PSC2_2 PSC2_3 PSC2_4 PSC3_0 PSC3_1 PSC3_2 PSC3_3 PSC3_4 PSC3_5 PSC3_6 PSC3_7 PSC3_8 PSC3_9 TxD, Sdata_out, MOSI, TX RxD, Sdata_in, MISO, TX Mclk, Sync, RTS BitClk, SCK, CTS Frame, SS, CD TxD, Sdata_out, MOSI, TX RxD, Sdata_in, MISO, TX Mclk, Sync, RTS BitClk, SCK, CTS Frame, SS, CD USB_OE, TxDS, TX USB_TXN, RxD, RX USB_TXP, BitClk, RTS USB_RXD, Frame, SS, CTS USB_RXP, CD USB_RXN USB_PRTPWR, Mclk, MOSI USB_SPEED. MISO USB_SUPEND, SS USB_OVRCNT, SCK I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO GPIO/TIMER GPIO_WKUP_6 GPIO_WKUP_7 TIMER_0 MEM_CS1 I/O I/O I/O VDD_MEM_IO VDD_IO VDD_IO DRV16_MEM DRV8 DRV4 TTL TTL TTL PULLUP_MEM DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 TTL TTL TTL Schmitt TTL TTL TTL TTL Schmitt TTL TTL TTL Schmitt TTL TTL TTL TTL TTL TTL TTL Output Driver Type DRV4 Input Type Schmitt Pull-up/ down
MPC5200B Data Sheet, Rev. 1 66 Freescale Semiconductor
Package Description
Table 52. MPC5200B Pinout Listing (continued)
Name TIMER_1 TIMER_2 TIMER_3 TIMER_4 TIMER_5 TIMER_6 TIMER_7 MOSI MISO SS SCK Alias Type I/O I/O I/O I/O I/O I/O I/O Power Supply VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO Clock SYS_XTAL_IN SYS_XTAL_OUT RTC_XTAL_IN RTC_XTAL_OUT Input Output Input Output VDD_IO VDD_IO VDD_IO VDD_IO Misc PORRESET HRESET SRESET IRQ0 IRQ1 IRQ2 IRQ3 Input I/O I/O I/O I/O I/O I/O VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO DRV4 DRV8_OD1 DRV8_OD1 DRV4 DRV4 DRV4 DRV4 Schmitt Schmitt Schmitt TTL TTL TTL TTL Output Driver Type DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 DRV4 Input Type TTL TTL TTL TTL TTL TTL TTL Pull-up/ down
Test/Configuration SYS_PLL_TPA TEST_MODE_0 TEST_MODE_1 TEST_SEL_0 TEST_SEL_1 JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST TCK TDI TDO TMS TRST I/O Input Input I/O I/O Input Input I/O Input Input VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO DRV4 DRV4 DRV4 DRV4 DRV8 DRV4 DRV4 DRV8 DRV4 DRV4 TTL TTL TTL TTL TTL Schmitt TTL TTL TTL TTL PULLUP PULLUP PULLUP PULLUP PULLUP
Power and Ground VDD_IO -
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 67
System Design Information
Table 52. MPC5200B Pinout Listing (continued)
Name VDD_MEM_IO VDD_CORE VSS_IO/CORE SYS_PLL_AVDD CORE_PLL_AVDD Alias Type Power Supply Output Driver Type Input Type Pull-up/ down
NOTES: 1 All "open drain" outputs of the MPC5200B are actually regular three-state output drivers with the output data tied low and the output enable controlled. Thus, unlike a true open drain, there is a current path from the external system to the MPC5200B I/O power rail if the external signal is driven above the MPC5200B I/O power rail voltage.
5
5.1
System Design Information
Power Up/Down Sequencing
Figure 51 shows situations in sequencing the I/O VDD (VDD_IO), Memory VDD (VDD_IO_MEM), PLL VDD (PLL_AVDD), and Core VDD (VDD_CORE).
MPC5200B Data Sheet, Rev. 1 68 Freescale Semiconductor
System Design Information
DC Power Supply Voltage
3.3V
VDD_IO, VDD_IO_MEM (SDR) VDD_IO_MEM (DDR)
2.5V
1
1.5V
VDD_CORE, PLL_AVDD
2
0 Time
Note:
1. VDD_CORE should not exceed VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V at any time, including power-up. 2. It is recommended that VDD_CORE/PLL_AVDD should track VDD_IO/VDD_IO_MEM up to 0.9 V then separate for completion of ramps. 3. Input voltage must not be greater than the supply voltage (VDD_IO) VDD_IO_MEM, VDD_CORE, or PLL_AVDD) by more than 0.5 V at any time,
Figure 51. Supply Voltage Sequencing
The relationship between VDD_IO_MEM and VDD_IO is non-critical during power-up and power-down sequences. Both VDD_IO_MEM (2.5 V or 3.3 V) and VDD_IO are specified relative to VDD_CORE.
5.1.1
Power Up Sequence
If VDD_IO/VDD_IO_MEM are powered up with the VDD_CORE at 0V, the sense circuits in the I/O pads will cause all pad output drivers connected to the VDD_IO/VDD_IO_MEM to be in a high-impedance state. There is no limit to how long after VDD_IO/VDD_IO_MEM powers up before VDD_CORE must power up. VDD_CORE should not lead the VDD_IO, VDD_IO_MEM or PLL_AVDD by more than 0.4 V during power ramp up or there will be high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond to avoid turning on the internal ESD protection clamp diodes. The recommended power up sequence is as follows: Use one microsecond or slower rise time for all supplies. VDD_CORE/PLL_AVDD and VDD_IO/VDD_IO_MEM should track up to 0.9 V and then separate for the completion of ramps with VDD_IO/VDD_IO_MEM going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 69
System Design Information
5.1.2
Power Down Sequence
If VDD_CORE/PLL_AVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers to be in a high impedance state. There is no limit on how long after VDD_CORE and PLL_AVDD power down before VDD_IO or VDD_IO_MEM must power down. VDD_CORE should not lag VDD_IO, VDD_IO_MEM, or PLL_AVDD going low by more than 0.5V during power down or there will be undesired high current in the ESD protection diodes. There are no requirements for the fall times of the power supplies. The recommended power down sequence is as follows: Drop VDD_CORE/PLL_AVDD to 0V.
Drop VDD_IO/VDD_IO_MEM supplies.
5.2
System and CPU Core AVDD Power Supply Filtering
Each of the independent PLL power supplies require filtering external to the device. The following drawing is a recommendation for the required filter circuit.
Power Supply source
10 10 F
<1 AVDD device pin 200-400 pF
Figure 52. Power Supply Filtering
5.3
5.3.1
Pull-up/Pull-down Resistor Requirements
Pull-down Resistor Requirements for TEST pins
The MPC5200B requires external pull-up or pull-down resistors on certain pins.
The MPC5200B requires pull-down resistors on the test pins TEST_MODE_0, TEST_MODE_1, TEST_SEL_1.
5.3.2
Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local Bus specification [4]. This is also required for MOST/Graphics and Large Flash Mode. PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain stable values when no agent is actively driving the bus. This includes
MPC5200B Data Sheet, Rev. 1 70 Freescale Semiconductor
System Design Information
PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL, PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
5.3.3
Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode.
5.3.4
.Pull-up/Pull-down
Requirements for MEM_MDQS Pins (DDR
16-bit Mode)
The MEM_MDQS[1:0] signals are not used in DDR 16-bit mode and require pull-down resistors.
5.4
JTAG
The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the MPC5200B's embedded Freescale (formerly Motorola) MPC603e e300 processor. This interface provides a means for executing test routines and for performing software development and debug functions.
5.4.1
JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1 specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset performance, the JTAG_TRST signal must be asserted during power-on reset.
5.4.1.1
JTAG_TRST and PORRESET
The JTAG interface can control the direction of the MPC5200B I/O pads via the boundary scan chain. The JTAG module must be reset before the MPC5200B comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released. For more details refer to the Reset and JTAG Timing Specification.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 71
System Design Information
PORRESET
required assertion of JTAG_TRST optional assertion of JTAG_TRST
JTAG_TRST
Figure 53. PORRESET vs. JTAG_TRST
5.4.1.2
Connecting JTAG_TRST
The wiring of the JTAG_TRST depends on the existence of a board-related debug interface. (see below) Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the MPC5200B.
5.4.2
e300 COP/BDM Interface
There are two possibilities to connect the JTAG interface: using it with a COP connector and without a COP connector.
5.4.2.1
Boards Interfacing the JTAG Port via a COP Connector
The MPC5200B functional pin interface and internal logic provides access to the embedded e300 processor core through the Freescale (formerly Motorola) standard COP/BDM interface. Table 53 gives the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order.
Table 53. COP/BDM Interface Signals
BDM Pin # 16 15 14 13 12 11 10 9 8 MPC5200B I/O Pin -- TEST_SEL_0 -- HRESET -- SRESET -- JTAG_TMS -- BDM Connector GND ckstp_out KEY hreset GND sreset N/C tms N/C -- 100k Pull-Up -- -- Internal Pull Up/Down -- -- -- External Pull Up/Down -- -- -- 10k Pull-Up -- 10k Pull-Up -- 10k Pull-Up -- I/O (1) -- I -- O -- O -- O --
MPC5200B Data Sheet, Rev. 1 72 Freescale Semiconductor
System Design Information
Table 53. COP/BDM Interface Signals (continued)
BDM Pin # 7 6 5 4 3 2 1 NOTES:
1. With respect to the emulator tool's perspective: Input is really an output from the embedded e300 core. Output is really an input to the core. From the board under test, power sense for chip power. HALTED is not available from e300 core. Input to the e300 core to enable/disable soft-stop condition during breakpoints. MPC5200B internally ties CORE_QACK to GND in its normal/functional mode (always asserted).
MPC5200B I/O Pin JTAG_TCK -- See Note
(3)
BDM Connector tck VDD (2)
Internal Pull Up/Down 100k Pull-Up -- -- 100k Pull-Up 100k Pull-Up
External Pull Up/Down 10k Pull-Up -- -- 10k Pull-Up 10k Pull-Up -- --
I/O (1) O -- I O O O I
.
halted trst tdi
(3)
JTAG_TRST JTAG_TDI See Note
(4)
.
qack
(4)
-- --
JTAG_TDO
tdo
2. 3. 4.
For a board with a COP (common on-chip processor) connector, which accesses the JTAG interface and which needs to reset the JTAG module, simply wiring JTAG_TRST and PORRESET is not recommended. To reset the MPC5200B via the COP connector, the HRESET pin of the COP should be connected to the HRESET pin of the MPC5200B. The circuitry shown in Figure 54 allows the COP to assert HRESET or JTAG_TRST separately, while any other board sources can drive PORRESET.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 73
System Design Information
PORRESET
PORRESET HRESET VDD VDD 10Kohm 10Kohm TRST JTAG_TRST TMS 10Kohm VDD JTAG_TMS TCK VDD 10Kohm VDD JTAG_TDI 10Kohm VDD JTAG_TCK SRESET VDD 4 Key 14 9 12
MPC5200B
COP Header
13 11 16 HRESET SRESET 10Kohm
COP Connector Physical Pinout
1 3 5 7 9 11 13 15 2 4 6 8
7 10 12 K 16 15 1 Key 3 6 (2)
TDI
CKSTP_OUT TDO
TEST_SEL_0 JTAG_TDO
halted 5 (3) NC (4) qack 2 NC 10 8 NC NC
Figure 54. COP Connector Diagram
5.4.2.2
Boards Without COP Connector
If the JTAG interface is not used, JTAG_TRST should be tied to PORRESET, so that it is asserted when the system reset signal (PORRESET) is asserted. This ensures that the JTAG scan chain is initialized during power on. Figure 55 shows the connection of the JTAG interface without COP connector.
MPC5200B Data Sheet, Rev. 1 74 Freescale Semiconductor
Ordering Information
PORRESET
PORRESET HRESET VDD 10Kohm VDD SRESET
MPC5200B
HRESET SRESET
10Kohm
JTAG_TRST 10Kohm VDD JTAG_TMS 10Kohm VDD JTAG_TCK 10Kohm VDD JTAG_TDI TEST_SEL_0 JTAG_TDO
Figure 55. JTAG_TRST Wiring for Boards without COP Connector
6
Ordering Information
Table 54. Ordering Information
Part Number * MPC5200VR400B MPC5200CVR400B SPC5200VVR266B SPC5200CBV400B SPC5200CVR400B Speed 400 400 266 400 400 Ambient Temp 0C to 70C -40C to 85C -40C to 105C -40C to 85C -40C to 85C Qualification ** Commercial Industrial Automotive - AEC Automotive - AEC Automotive - AEC Packaging *** RoHS & pb-free RoHS & pb-free RoHS & pb-free Standard RoHS & pb-free
* Shipped in trays. Add "R2" suffix for Tape & Reel. * * Commercial Qualified to <250PPM level. Industrial/Automotive Qualified to AEC-Q100. Automotive has Zero Defect flow. * * * Standard is halide-free with pb solder balls.
MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 75
Document Revision History
7
Document Revision History
Table 55. Document Revision History
Rev. No. 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Substantive Change(s) First Preliminary release with some TBD's in spec tables (3/2005) Updates to Ethernet, LPC, Power Down, Input Leakage, Ordering Information (7/2005) Updates to LPC timing and Pull-up/Pull-down Requirements (8/2005) Updates to Power dissipation (8/2005) Applied marked-up hard copy edits and Tabasco excel edits (10/2005) Changed the alias name for ETH_2 to USB_TXP, RTS, TXD[1] in Table 52. Table 2: * Two rows were added at the bottom that with ranges from -40 to +105 and -40 to +125 * The rows from -40 to +85 and -40 to +115 were footnoted with "Maximum e300 core operating frequency is 400 MHz. * The rows from -40 to +115 and -40 to +125 were footnoted with "Maximum e300 core operating frequency is 266 MHz Table 54: * Eliminated all part numbers for 466 MHz * Eliminated all "standard" package part numbers except for the one automotive grade at 400 MHz * MPC5200CVR266B was changed to MPC5200CVR400B with the speed of 400 MHz Table 12: 466 MHz was changed to 400 MHz; removed 2 blank pages
Table 55 provides a revision history for this hardware specification.
1
For more detailed information, refer to the following documentation: 1. MPC5200B User Manual MPC5200BUM 2. "PowerPC Microprocessor Family: The Programming Environments for 32-bit Microprocessors," Rev. 2: MPCFPE32B/AD 3. G2 Core Reference Manual, Rev. 0: G2CORERM/D 4. "PCI Local Bus Specification," Revision 2.2, December 18, 1998 5. "ANSI ATA-4 Specification" 6. "IEEE 802.3 Specification (ETHERNET)"
MPC5200B Data Sheet, Rev. 1 76 Freescale Semiconductor
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MPC5200B Data Sheet, Rev. 1 Freescale Semiconductor 77
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MPC5200BDS Rev. 1, 1/2006

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